High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/su...

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Published inInternational Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) pp. 19.5.1 - 19.5.4
Main Authors Kedzierski, J., Fried, D.M., Nowak, E.J., Kanarsky, T., Rankin, J.H., Hanafi, H., Natzle, W., Boyd, D., Ying Zhang, Roy, R.A., Newbury, J., Chienfan Yu, Qingyun Yang, Saunders, P., Willets, C.P., Johnson, A., Cole, S.P., Young, H.E., Carpenter, N., Rakowski, D., Rainey, B.A., Cottrell, P.E., Ieong, M., Wong, H.-S.P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
CMOS logic circuits
Epitaxial growth
Etching
FinFETs
Implants
Logic devices
Microelectronics
MOS devices
MOSFETs
Silicon
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Summary:Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.
ISBN:0780370503
9780780370500
DOI:10.1109/IEDM.2001.979530