Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

3D simulations have been performed to study the impact of self-heating in SOI on circuits. Using multiple finger structures we have established bounds on the magnitude of the heat increase and its behavior with device scaling. This allows circuit designers to quickly evaluate temperature variations...

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Bibliographic Details
Published in2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207) pp. 101 - 102
Main Authors Sinha, S.P., Pelella, M., Tretz, C., Riccobene, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
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