Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

3D simulations have been performed to study the impact of self-heating in SOI on circuits. Using multiple finger structures we have established bounds on the magnitude of the heat increase and its behavior with device scaling. This allows circuit designers to quickly evaluate temperature variations...

Full description

Saved in:
Bibliographic Details
Published in2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207) pp. 101 - 102
Main Authors Sinha, S.P., Pelella, M., Tretz, C., Riccobene, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Circuit simulation
CMOS technology
Cogeneration
Conducting materials
Cooling
Fingers
Integrated circuit interconnections
MOSFETs
Temperature sensors
Thermal conductivity
Online AccessGet full text

Cover

More Information
Summary:3D simulations have been performed to study the impact of self-heating in SOI on circuits. Using multiple finger structures we have established bounds on the magnitude of the heat increase and its behavior with device scaling. This allows circuit designers to quickly evaluate temperature variations in real circuits under various operating conditions. for various device sizes and subject to different current density thanks to simple scaling of the presented results. The approach gives a simple and efficient way to take into account self heating in circuit optimization. In addition. contrary to previous studies, we have found that the heat predominantly flows through the buried oxide.
ISBN:0780367391
9780780367395
ISSN:1078-621X
2577-2295
DOI:10.1109/SOIC.2001.958006