A 1.2 V 500 MHz 32-bit carry-lookahead adder

In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-fu...

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Published inICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Vol. 2; pp. 765 - 768 vol.2
Main Authors Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Adders
Circuits
Clocks
CMOS technology
Latches
Logic gates
Low voltage
MOS devices
MOSFETs
Threshold voltage
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Summary:In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 /spl mu/m 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.
ISBN:0780370570
9780780370579
DOI:10.1109/ICECS.2001.957587