A sub 40-nm body thickness n-type FinFET

• Published in: Device Research Conference. Conference Digest (Cat. No.01TH8561) pp. 24 - 25
• Main Authors: Fried, D.M., Johnson, A.P., Nowak, E.J., Rankin, J.H., Willets, C.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: Electrodes; Etching; FinFETs; Gate leakage; Implants; Lithography; MOSFETs; Oxidation; Silicon; Voltage
• ISBN: 9780780370142; 0780370147
• DOI: 10.1109/DRC.2001.937857

We experimentally demonstrate near-ideal subthreshold behavior of fully-depleted fin-style double-gate n-type MOSFETs and the best measured transconductance Gm-sat = 72 S/m (>400 S/m intrinsic) for sub-40 nm n-type FinFETs reported. This silicon nFET exhibits experimental ideality n = 1.13, in good agreement with the deviation from unity expected due only to source/drain coupling. These results comprise the best behavior for 100 nm-scale double-gate nFETs in terms of channel subthreshold characteristics and gate leakage observed experimentally to date. Hisamoto et al. (1989) introduced experimental results on doubld-gate silicon MOSFETs in which the channel is formed by etching single-crystal silicon to leave a vertical fin standing, forming a gate which wraps around the fin, with source and drain regions on the two ends of the fin. This basic idea was further refined to sub-50 nm n-type MOSFETs and then extended to sub-50 nm p-type MOSFETs. Using simplified fabrication techniques, we demonstrate improved behavior, from an intrinsic channel point of view, of the nFET work, using conventional CMOS integration on n-type FinFETs.