Full CMP integration of CVD TiN damascene sub-0.1-/spl mu/m metal gate devices for ULSI applications

• Published in: IEEE transactions on electron devices Vol. 48; no. 8; pp. 1816 - 1821
• Main Authors: Ducroquet, F., Achard, H., Coudert, F., Previtali, B., Lugand, J.-F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.2001
• Subjects: Integrated circuit metallization

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/...