Full CMP integration of CVD TiN damascene sub-0.1-/spl mu/m metal gate devices for ULSI applications

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 48; no. 8; pp. 1816 - 1821
Main Authors Ducroquet, F., Achard, H., Coudert, F., Previtali, B., Lugand, J.-F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
Format Journal Article
LanguageEnglish
Published IEEE 01.08.2001
Subjects
Integrated circuit metallization
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Summary:Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/spl mu/m gate transistors up to 0.6-mm/sup 2/ capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO/sub 2/).
ISSN:0018-9383
1557-9646
DOI:10.1109/16.936712