Statistical SPICE analysis of a 0.18 /spl mu/m CMOS digital/analog technology during process development

• Published in: ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153) pp. 19 - 23
• Main Authors: Rankin, N.S., Chun Ng, Leang Sern Ee, Boyland, F., Quek, E., Leung Ying Keung, Walton, A.J., Redford, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: CMOS technology; Electric variables measurement; Length measurement; Monte Carlo methods; Parameter extraction; Process control; Semiconductor device modeling; SPICE; Statistical distributions; Testing
• ISBN: 9780780365117; 0780365119
• DOI: 10.1109/ICMTS.2001.928631

This paper gives details of a methodology to extract statistical SPICE models on a developing deep sub micron CMOS technology. The approach uses a TCAD framework which integrates process, device, parameter extraction, and statistics software. The TCAD tools are calibrated by physical and electrical measurements on transistor test structures with different channel lengths. Once calibrated, a Monte Carlo experiment is run on all process control input parameters with realistic variations and the results then compared to in-line and E-test distributions. When satisfied that the variance in TCAD and measured distributions match, the framework can be used to extract BSIM3v3.2 parameters to generate statistical models. Multivariate statistics is used to determine the key process parameters which need to be controlled in-line to minimize device variation. This methodology is demonstrated using Chartered Semiconductor Manufacturing Ltd's 0.18 /spl mu/m CMOS core logic technology.