Investigation of the Trap States and V} Instability in LPCVD Si3N4/AlGaN/GaN MIS-HEMTs with an In-Situ Si3N4 Interfacial Layer

• Published in: IEEE transactions on electron devices Vol. 66; no. 8; pp. 3290 - 3295
• Main Authors: Sun, Hui, Wang, Maojun, Yin, Ruiyuan, Chen, Jianguo, Xue, Shuai, Luo, Jiansheng, Hao, Yilong, Chen, Dongmin
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.2019
• Subjects: AlGaN/GaN; Dielectrics; Gallium nitride; HEMTs; in-situ Si₃N; Logic gates; low-pressure chemical vapor deposition (LPCVD) Si₃N; metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT); MOCVD; quasi-static (QS) C–V; Silicon; Surface treatment; trap states; VTH instability
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2919246

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si 3 N 4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si 3 N 4 (30 nm) in AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si 3 N 4 /(Al)GaN interface and the effect on threshold voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {TH}} </tex-math></inline-formula>) instability and dynamic <inline-formula> <tex-math notation="LaTeX">{R}_{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> in the MIS-HEMTs with/without the in-situ Si 3 N 4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) <inline-formula> <tex-math notation="LaTeX">{C} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{V} </tex-math></inline-formula> (QSCV), time-of-fly (TOF) stress/measure, and QS <inline-formula> <tex-math notation="LaTeX">{I}_{\text {D}} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{V}_{\text {DS}} </tex-math></inline-formula> methods. It is founded that the in-situ Si 3 N 4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better <inline-formula> <tex-math notation="LaTeX">{V}_{\text {TH}} </tex-math></inline-formula> stability and lower <inline-formula> <tex-math notation="LaTeX">{R} _{ \mathrm{\scriptscriptstyle ON},\text {D}}/{R} _{ \mathrm{\scriptscriptstyle ON},\text {S}} </tex-math></inline-formula> ratio are observed in devices with the in-situ Si 3 N 4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.