Formal verification of globally-iterated and locally-non-iterated finite state machines

Formal verification of hardware has significantly gained in popularity as an alternative to testing and simulation in hardware design. Recently we introduced a new methodology for verification of non-iterated systems. The technique is based on the inductively defined notion of a series-parallel pose...

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Bibliographic Details
Published in42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356) Vol. 1; pp. 202 - 205 vol. 1
Main Authors Ivanov, L., Nunna, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Automata
Computational modeling
Computer science
Computer simulation
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Formal verification
Hardware
Logic gates
Sequential circuits
Testing
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Summary:Formal verification of hardware has significantly gained in popularity as an alternative to testing and simulation in hardware design. Recently we introduced a new methodology for verification of non-iterated systems. The technique is based on the inductively defined notion of a series-parallel poset. In this paper we extend the notion of series-parallel posets to allow the modeling of systems involving global iteration. For this class of systems we present a verification algorithm, and discuss its foundation.
ISBN:0780354915
9780780354913
DOI:10.1109/MWSCAS.1999.867243