A Digital PLL Based 2nd-Order Δ∑ Bandpass Time-Interleaved ADC

This paper presents a time-interleaved (TI) VCObased band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current starved ring-oscillator as integrator which provides inherent multi-bit quantization...

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Published in2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 286 - 289
Main Authors Chandrasekaran, Sanjeev Tannirkulam, Sanyal, Arindam
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2018
Subjects
Calibration
Clocks
Gain
Quantization (signal)
Receivers
Timing
Voltage-controlled oscillators
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Summary:This paper presents a time-interleaved (TI) VCObased band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current starved ring-oscillator as integrator which provides inherent multi-bit quantization. Thus, the proposed band-pass ADC does not need op-amps for integration and consumes low power and area. The proposed ADC is designed in 65nm CMOS and Matlab and Spectre simulations were performed to characterize the ADC. The proposed ADC achieves 61dB SNDR while consuming 0.44mW and has a Walden FoM of 63fJ/conv. step.
ISSN:1558-3899
DOI:10.1109/MWSCAS.2018.8623928