An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin

The authors present an 18 Mb CMOS SRAM which operates at 833 MHz with 1.67 Gb/s/pin. The 114.4 mm/sup 2/ die consumes 1.5 W and is fabricated in a 0.18 /spl mu/m CMOS process with four levels of copper interconnect. The SRAM operates in two user-selectable double-data-rate modes (DDR and DDR2). High...

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Published in2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) pp. 266 - 267
Main Authors Pilo, H., Allen, A., Covino, J., Hansen, P., Lamphier, S., Murphy, C., Traver, T., Yee, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Clocks
CMOS process
Copper
Decoding
Delay
Latches
Microelectronics
Random access memory
Switches
Timing
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Summary:The authors present an 18 Mb CMOS SRAM which operates at 833 MHz with 1.67 Gb/s/pin. The 114.4 mm/sup 2/ die consumes 1.5 W and is fabricated in a 0.18 /spl mu/m CMOS process with four levels of copper interconnect. The SRAM operates in two user-selectable double-data-rate modes (DDR and DDR2). High-frequency operation is achieved by solving three frequency-limiting issues identified in previous SRAM designs: managing data timing constraints associated with high-frequency operation in a high density SRAM core; maintaining coherency between SRAM output data timings and echo clock timings; and delivering symmetric data windows for 1 s and 0 s across a wide range of output driver supply levels.
ISBN:0780358538
9780780358539
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2000.839778