A 1 GHz single-issue 64 b PowerPC processor

• Published in: 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056) pp. 92 - 93
• Main Authors: Hofstee, P., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., Kojima, N., Kwon, O., Lee, K., Meltzer, D., Nowka, K., Park, J., Peter, J., Posluszny, S., Shapiro, M., Silberman, J., Takahashi, O., Weinberger, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Circuit testing; Clocks; CMOS process; Copper; Delay; Energy management; Frequency; Integrated circuit interconnections; Memory management; Stress control
• ISBN: 0780358538; 9780780358539
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2000.839705

This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS. Nominal processor clock frequency is 1.0 GHz. At the fast end of the process distribution the processor reaches 1.15 GHz (1.87 V, 101/spl deg/C, 112 W). As in a previous design, nearly the entire processor is implemented using delayed-reset and self-resetting dynamic circuit macros. New contributions include: (1) a fully pipelined, four execution-stage IEEE double-precision floating-point unit (FPU) with fused multiply-add. 2) Sum-addressed memory management units (MMUs) and 64 kB 2-cycle caches. (3) Support for the full 64 b PowerPC instruction set. (4) Dynamic PLA-based control. (5) A microarchitecture and floorplan that balances critical paths. (6) Delayed-reset dynamic circuits that support stress testing (burn-in). 7) Improved clock generation and distribution.