Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee

The eight papers in this session highlight developments in neuromorphic acceleration, clocking circuits and security building blocks. A highlighted paper demonstrates a neuromorphic accelerator with stochastic synapses and embedded online reinforcement learning in autonomous micro-robots. The clocki...

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Bibliographic Details
Published in2018 IEEE International Solid-State Circuits Conference - (ISSCC) pp. 116 - 117
Main Authors Shin, Youngmin, Restle, Phillip, Beigne, Edith
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2018
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Summary:The eight papers in this session highlight developments in neuromorphic acceleration, clocking circuits and security building blocks. A highlighted paper demonstrates a neuromorphic accelerator with stochastic synapses and embedded online reinforcement learning in autonomous micro-robots. The clocking papers presented demonstrate an all-digital multiplying DLL, a synthesizable fractional-N PLL and a synthesizable period-jitter sensor. Improvements to random-number generators and physically unclonable functions provide lower error rates and lossless stabilization by a novel remapping scheme.
ISSN:2376-8606
DOI:10.1109/ISSCC.2018.8310211