A four-transistor CMOS SRAM cell

• Published in: 1999 IEEE Africon. 5th Africon Conference in Africa (Cat. No.99CH36342) Vol. 2; pp. 1173 - 1176 vol.2
• Main Authors: Joubert, T.-H., Seevinck, E., du Plessis, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: CMOS logic circuits; CMOS process; CMOS technology; Inverters; Monitoring; MOSFETs; Random access memory; SRAM chips; Thin film transistors; Threshold voltage

In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is propose...