A four-transistor CMOS SRAM cell

In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is propose...

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Bibliographic Details
Published in1999 IEEE Africon. 5th Africon Conference in Africa (Cat. No.99CH36342) Vol. 2; pp. 1173 - 1176 vol.2
Main Authors Joubert, T.-H., Seevinck, E., du Plessis, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
CMOS logic circuits
CMOS process
CMOS technology
Inverters
Monitoring
MOSFETs
Random access memory
SRAM chips
Thin film transistors
Threshold voltage
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Summary:In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper.
ISBN:0780355466
9780780355460
DOI:10.1109/AFRCON.1999.821945