23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

• Published in: 2017 IEEE International Solid-State Circuits Conference (ISSCC) pp. 400 - 401
• Main Authors: Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2017
• Subjects: Clocks; Decision feedback equalizers; Delays; Mobile communication; Random access memory; Receivers; Transceivers
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2017.7870430

Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate that can be handled by the receiver (RX); the maximum data rate reported is below 10Gb/s with a supply voltage of 0.8V in 65nm CMOS [2-4]. In a conventional RX at a low-supply voltage, the maximum data rate is limited by the small g m /C of the RX front-end circuit. To eliminate this g m /C constraint, this work proposes a time-based RX for 12Gb/s operation at 0.8V.