8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz

• Published in: Digest of technical papers - IEEE International Solid-State Circuits Conference pp. 154 - 155
• Main Authors: Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2017
• Subjects: Clocks; Interpolation; Linearity; Phase locked loops; Phase noise; Quantization (signal)
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2017.7870307

There continue to be efforts to develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several approaches for fully synthesized digital PLLs [1-4] via gate-level implementation of a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Though automated layout has been achieved, the lock-range and phase-noise performance are subject to process variations. Critical performance-limiting blocks, such as the TDC and DCO, should be carefully designed with analog circuit simulators, diluting the inherent benefits of digital design. This work presents a highly programmable and synthesizable TDC- and DCO-less fractional-N PLL architecture, employing a phase-locked direct-digital synthesizer (PLDDS) driven by a free-running oscillator. The PLDDS design is specified entirely in a register-transfer level (RTL) hardware-description language (HDL) without any need for analog simulation.