Low-power behavioral synthesis optimization using multiple precision arithmetic

• Published in: Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) pp. 568 - 573
• Main Authors: Ercegovac, M., Kirovski, D., Potkonjak, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Computer aided instruction; Concurrent computing; Fixed-point arithmetic; Integrated circuit synthesis; Multimedia communication; Optimization; Parallel processing; Power dissipation; Power generation; Timing
• ISBN: 1581130929; 9781581130928
• DOI: 10.1109/DAC.1999.781379

Many modern multimedia applications such as image and video processing are characterized by a unique combination of arithmetic and computational features: fixed-point arithmetic, a variety of short data types, high degree of instruction-level parallelism, strict timing constraints, and high computational requirements. Computationally intensive algorithms usually boost device's power dissipation which is often key to the efficiency of many communications and multimedia applications. Although recently virtually all general-purpose processors have been equipped with multiprecision operations, the current generation of behavioral synthesis tools for application-specific systems does not utilize this power/performance optimization paradigm. In this paper, we explore the potential of using multiple precision arithmetic units to effectively support synthesis of low-power application-specific integrated circuits. We propose a new architectural scheme for collaborate addition of sets of variable precision data. We have developed a novel resource allocation and computation assignment methodology for a set of multiple precision arithmetic units. The optimization algorithms explore the trade-off of allocating low-width bus structures and executing multiple-cycle operations. Experimental results indicate strong advantages of the proposed approach.