Symbol timing recovery using digital spectral line method for 16-CAP VDSL system
This paper presents a new digital spectral line symbol timing recovery method for 16-CAP VDSL system. The proposed method resolves the digital implementation issues of the analog counterpart in two ways: (i) it avoids the costly linear phase bandpass filter that would otherwise be necessary, and (ii...
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Published in | IEEE GLOBECOM 1998 (Cat. NO. 98CH36250) Vol. 6; pp. 3467 - 3472 vol.6 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
1998
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Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a new digital spectral line symbol timing recovery method for 16-CAP VDSL system. The proposed method resolves the digital implementation issues of the analog counterpart in two ways: (i) it avoids the costly linear phase bandpass filter that would otherwise be necessary, and (ii) it resolves the bandwidth expansion problem by using a single-sided pre-filter pair. With the architectural simplicity, its lower-frequency sampling clock offers an inexpensive implementation for the high speed timing recovery. Simulation shows that the jitter performance of the proposed method approaches to the theoretical limit especially for the transmission distance of less than 200 meters. |
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ISBN: | 0780349849 9780780349841 |
DOI: | 10.1109/GLOCOM.1998.775845 |