A 14 b 100 Msample/s CMOS DAC designed for spectral performance

At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m C...

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Bibliographic Details
Published in1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) pp. 148 - 149
Main Authors Bugeja, A.R., Bang-Sup Song, Rakers, P.L., Gillig, S.F.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Capacitors
Clocks
CMOS process
Decoding
Frequency
Linearity
Optical wavelength conversion
Switches
Switching circuits
Threshold voltage
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Summary:At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.
ISBN:9780780351264
0780351266
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1999.759168