A 1.1 nm oxide equivalent gate insulator formed using TiO/sub 2/ on nitrided silicon

Tunneling leakage limits the scaling of SiO/sub 2/ to about 1.5 nm. Well behaved transistors have previously been made with MOCVD-deposited TiO/sub 2/ using the thermal decomposition of titanium tetrakis isopropoxide. However, after the required O/sub 2/ anneal, these devices have a 2.5 nm amorphous...

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Bibliographic Details
Published inInternational Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) pp. 1038 - 1040
Main Authors Ho, B., Ma, T., Campbell, S.A., Gladfelter, W.L.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Amorphous materials
Annealing
Capacitance
Hydrogen
Insulation
Morphology
Silicon
Thermal decomposition
Titanium
Tunneling
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Summary:Tunneling leakage limits the scaling of SiO/sub 2/ to about 1.5 nm. Well behaved transistors have previously been made with MOCVD-deposited TiO/sub 2/ using the thermal decomposition of titanium tetrakis isopropoxide. However, after the required O/sub 2/ anneal, these devices have a 2.5 nm amorphous interfacial layer which severely limits the capacitance. We have synthesized nitrato titanium (Ti(NO/sub 3/)/sub 4/ or NT) as a hydrogen and carbon free deposition. In an effort to obtain low leakage, /spl sim/1.0 nm GOE slacks, we have used NT to deposit progressively thinner TiO/sub 2/ layers on silicon that has been thermally nitrided at 850/spl deg/C in NH/sub 3/ at 10 torr. The article shows film morphology representative of device deposition (500/spl deg/C). TiO/sub 2/ deposition rates were /spl sim/0.8 nm/min. A post deposition anneal of 700/spl deg/C was done in N/sub 2/. These anatase films are stable up to approximately 850/spl deg/C. Capacitors were made by Pt sputtering, photolithography, and ion milling. A final 450/spl deg/C H/sub 2/ anneal was done on all samples.
ISBN:0780347749
9780780347748
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1998.746533