19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation

• Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 332 - 333
• Main Authors: Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2016
• Subjects: Calibration; Detectors; Jitter; Phase locked loops; Resistance; Solid state circuits; Temperature measurement
• ISBN: 1467394661; 9781467394666
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2016.7418042

Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated together, the power supply noise may degrade the jitter performance of the PLL. To lower the supply-noise sensitivity of a PLL, several approaches [1-5] have been proposed. A passive decoupling capacitor and/or a low-dropout (LDO) regulator [1] can be used to suppress the supply noise. However, the decoupling capacitor occupies large area and the LDO requires additional power and area. In [2], a calibration mechanism is used to close and open the loop on an alternating basis, increasing the settling time. In [3], an extra foreground frequency calibration is needed to ensure the PLL is at the correct sub-band and supply voltage - it may be susceptible to process, voltage and temperature (PVT) variations. The approach in [4] requires a low-frequency triangular signal generator, additional current sources, and active devices, increasing power and noise. In [5], two constant-gm bias circuits are used to cancel supply noise. However, it is sensitive to PVT variations, which may degrade the supply-noise suppression.