Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete I} Modeling Formalism

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I ds model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 63; no. 4; pp. 1416 - 1422
Main Authors Kejun Xia, McAndrew, Colin C., Grote, Bernhard
Format Journal Article
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Computational modeling
JFETs
Logic gates
Numerical models
P-n junctions
Robustness
Semiconductor device modeling
SPICE
semiconductor device modeling
SPICE
JFETs
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Summary:This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I ds model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for I ds and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2016.2521759