High voltage resistant ESD protection circuitry for 0.5 /spl mu/m CMOS OTP/EPROM programming pin

This work introduces new high voltage resistant ESD protection circuitry for the programming pin of a nonvolatile one time programmable silicided 0.5 /spl mu/m CMOS device. TLM, HBM, and MM0.75 /spl mu/H ESD stress measurements of this new design resulted in latch-up resistant protection circuitry w...

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Bibliographic Details
Published inElectrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347) pp. 96 - 103
Main Authors Schroder, H.-U., Van Steenwijk, G., Notermans, G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Breakdown voltage
Circuits
CMOS process
Diodes
Electrostatic discharge
EPROM
Nonvolatile memory
Protection
Resistors
Thyristors
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Summary:This work introduces new high voltage resistant ESD protection circuitry for the programming pin of a nonvolatile one time programmable silicided 0.5 /spl mu/m CMOS device. TLM, HBM, and MM0.75 /spl mu/H ESD stress measurements of this new design resulted in latch-up resistant protection circuitry with an ESD performance of more than 8.0 kV HBM and 950 V MM0.75 /spl mu/H.
ISBN:9781878303912
1878303910
DOI:10.1109/EOSESD.1998.737026