Plasma induced damage on sub-0.5 /spl mu/m MOSFETs using a CMOS driver as input protection

Plasma charging effects on a sub-0.5 /spl mu/m CMOS process with 90 /spl Aring/ gate oxide and triple layer metal was studied for plasma induced damage with diode and ESD protection schemes. The n and p channel transistors in a CMOS driver enabled discharging of positive and negative charges using t...

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Bibliographic Details
Published in1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100) pp. 100 - 103
Main Authors Gill, C., Porter, J., McEntarfer, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Antenna measurements
CMOS process
Diodes
Driver circuits
Electrostatic discharge
MOSFETs
Plasma devices
Plasma measurements
Plasma sources
Protection
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Summary:Plasma charging effects on a sub-0.5 /spl mu/m CMOS process with 90 /spl Aring/ gate oxide and triple layer metal was studied for plasma induced damage with diode and ESD protection schemes. The n and p channel transistors in a CMOS driver enabled discharging of positive and negative charges using the source-drain region as diodes. This study also showed that the p channel devices are more sensitive to plasma charging than n channels. The diode protection provided to the transistor gate reduced the magnitude of plasma process induced damage, but a large antenna ratio on protected gates was observed to produce measurable shifts in V/sub t/ and I/sub dsat/.
ISBN:0965157725
9780965157728
DOI:10.1109/PPID.1998.725584