Increased channel edge impact ionization in SOI MOSFET's and effects on device operation

• Published in: 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199) pp. 171 - 172
• Main Authors: Duan, F.L., Zhao, X., Ioannou, D.E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Circuit testing; Current measurement; Degradation; Fabrication; Hot carriers; Impact ionization; Latches; Life testing; MOSFETs; Voltage
• ISBN: 9780780345003; 0780345002
• ISSN: 1078-621X; 2577-2295
• DOI: 10.1109/SOI.1998.723166

Summary form only given. In SOI MOSFETs, the holes (for n-channel devices) generated by impact ionization near the drain can not be properly removed as in the case of bulk MOSFETs. Due to the confinement by the buried oxide inherent in a SOI structure, the holes generated through impact ionization redistribute in the floating body and enhance the impact ionization rate near the edges of the channel, increasing with increasing device width. This is experimentally evidenced by the measured lower single transistor latch on voltages and higher linear current degradation in typical fully depleted (FD) SOI MOSFETs, and a stronger kink effect in typical partially-depleted (PD) MOSFETs, as the device width increases. It is thus suggested that more attention should be paid to the edges of the device during design and fabrication, to decrease impact ionization and/or increase carrier recombination locally. Also, in contrast to bulk technology, circuit designers must be aware that devices of different widths may have different latch-up voltages and that the hot carrier device lifetime might be underestimated if the narrow devices are tested.