An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic (BL) LSI for a high-speed parallel processing system has been designed with a standard-cell approach, fabricated by a 0.8- mu m WN/sub x/ gate LDD MESFET process, and confirmed to be fully functional. The BL consists of 3376 logic-gates and a 76-b dual-port register file...

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Bibliographic Details
Published in11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium pp. 105 - 108
Main Authors Kameyama, A., Kawakyu, K., Sasaki, T., Seshita, T., Terada, T., Kitaura, Y., Toyoda, N., Maeda, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1989
Subjects
Circuit testing
Gallium arsenide
Large scale integration
Logic design
Logic testing
Parallel processing
Power dissipation
Radio frequency
Registers
Ultra large scale integration
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Summary:An 8-b slice GaAs bus logic (BL) LSI for a high-speed parallel processing system has been designed with a standard-cell approach, fabricated by a 0.8- mu m WN/sub x/ gate LDD MESFET process, and confirmed to be fully functional. The BL consists of 3376 logic-gates and a 76-b dual-port register file (RF) in a 7-mm*7-mm chip. A 10-ns cycle time has been achieved with a power dissipation of 7 W. By constructing a data transfer network with 48 GaAs BLs, it is possible to realize a data transfer rate of 4 Gb/s (32 b*120 Mcycle/s).< >
DOI:10.1109/GAAS.1989.69304