High speed, smart focal plane processing using integrated photodetectors and Si CMOS VLSI sigma delta analog to digital converters

We report on the first demonstration of a high frame rate smart pixel imaging system which uses an ADC for in each pixel in an 8x8 integrated detector array. The smart pixel architecture of this system enables frame rates up to 100 kfps operating in continuous imaging mode.

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Bibliographic Details
Published in1998 IEEE/LEOS Summer Topical Meeting. Digest. Broadband Optical Networks and Technologies: An Emerging Reality. Optical MEMS. Smart Pixels. Organic Optics and Optoelectronics (Cat. No.98TH8369) pp. IV/55 - IV/56
Main Authors YoungJoong Joo, Fike, S., Thomas, M., Kee Shik Chung, Brooke, M., Jokerst, N.M., Scott Wills, D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Charge coupled devices
Circuit testing
CMOS process
Delta-sigma modulation
Detectors
Optical imaging
Photodetectors
Signal to noise ratio
Smart pixels
Very large scale integration
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Summary:We report on the first demonstration of a high frame rate smart pixel imaging system which uses an ADC for in each pixel in an 8x8 integrated detector array. The smart pixel architecture of this system enables frame rates up to 100 kfps operating in continuous imaging mode.
ISBN:0780349539
9780780349537
DOI:10.1109/LEOSST.1998.690447