Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion i...

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Published in1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) pp. 74 - 75
Main Authors Bevk, J., Kuehne, S., Vaidya, H., Mansfield, W., Hobler, G., Boulin, D.M., Bolan, K., Chang, C.P., Cheung, K.P., Cirelli, R., Colonell, J.I., Frackoviak, J., Frei, M., Gruensfelder, C., Jacobson, D.C., Key, R.W., Klemens, F.P., Lai, W.Y.C., Lee, J.T.-C., Liu, C.T., Liu, R., Oh, M., Maynard, H.L., Monroe, D.P., Nalamasu, O., Pai, C.S., Santiesteban, R., Silverman, P.J., Tai, W.W., Timko, A., Vuong, H., Watson, G.P., Thoma, M.J., Clemens, J.T., Hillenius, S.J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Boron
CMOS process
CMOS technology
Fabrication
Implants
Jacobian matrices
MOS devices
Nitrogen
Space technology
Threshold voltage
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Summary:We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of L/sub eff/.
ISBN:0780347706
9780780347700
DOI:10.1109/VLSIT.1998.689205