2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

2 nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the desi...

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Bibliographic Details
Published in2014 Symposium on VLSI Circuits Digest of Technical Papers pp. 1 - 2
Main Authors Meterelliyoz, Mesut, Al-amoody, Fuad H., Arslan, Umut, Hamzaoglu, Fatih, Hood, Luke, Lal, Manoj, Miller, Jeffrey L., Ramasundar, Anand, Soltman, Dan, Wan Ifar, Yih Wang, Zhang, Kevin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Abstracts
Clocks
CMOS integrated circuits
CMOS technology
Optimization
Random access memory
Synchronization
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Summary:2 nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions.
ISBN:1479933279
9781479933273
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2014.6858415