Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems

This work proposes an automated methodology for optimizing FPGA-based many-core interconnect architectures. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible...

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Bibliographic Details
Published in2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1 - 4
Main Authors Cilardo, Alessandro, Fusella, Edoardo, Gallo, Luca, Mazzeo, Antonino
Format Conference Proceeding
LanguageEnglish
Published EDAA 01.03.2014
Subjects
Bridges
Computer architecture
Hardware
Integrated circuit interconnections
Schedules
System-on-chip
Topology
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Summary:This work proposes an automated methodology for optimizing FPGA-based many-core interconnect architectures. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism that can be exploited while keeping area costs low. The paper thoroughly describes the proposed approach and discusses a few case-studies showing the impact of the proposed technique.
ISSN:1530-1591
1558-1101
DOI:10.7873/DATE.2014.352