13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

• Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 238 - 239
• Main Authors: Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chang, George H., Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Natarajan, Sreedhar, Chang, Jonathan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2014
• Subjects: CMOS integrated circuits; Couplings; FinFETs; High K dielectric materials; Logic gates; Random access memory
• ISBN: 1479909181; 9781479909186
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2014.6757416

FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve better performance with lower SRAM V DDMIN . However, the quantized sizing of the channel width and length has drawbacks for conventional 6T-SRAM bitcell scaling. To minimize the bitcell area of the high-density SRAM bitcell, the number of fins (setting the channel width, W) of the pull-up PMOS (PU), passgate NMOS (PG) and pull-down NMOS (PD) transistors must be selected as 1:1:1. Since PU, PG, and PD have the same channel length (L), the ratio in geometry between the PU transistor and the PG transistor is equal to one. With the process variations, the strength of PU transistor can be much stronger than the PG transistor. A stronger PU transistor increases read stability of the SRAM bitcell but it degrades the write margin significantly and results in worse write-V DDMIN issue. Figure 13.5.1(a) shows a contention condition between PU and PG transistors of a 6T-SRAM bitcell for the write operation. During the write operation, the PU transistor impedes the ability of the PG transistor to pull the storage node (S) from V DD to ground. The bitcell may suffer a write failure at the stronger PU with weaker PG condition caused by the device variations. Two techniques have been proposed to improve the high density SRAM bitcell write V DDMIN : 1) negative bit-line voltage (NBL) to increase the strength of PG transistor and 2) lower cell V DD (LCV) to weaken PU transistor strength [1-5]. Compared to the conventional techniques, this work develops a suppressed-coupling-signal negative bitline (SCS-NBL) scheme and a write-recovery-enhancement lower-cell-V DD (WRE-LCV) scheme for write assist without the concern of reliability at higher V DD operating region. A comparison of the effectiveness of the two design techniques is also performed. Figure 13.5.1(b) shows the layout view of the high-density 6T-SRAM bit-cell with 0.07μm 2 area in a 16nm high-k metal-gate FinFET technology. To minimize area, we set the geometric ratio of PU, PG, and PD transistors all equal to one. With the two developed write-assist circuits, the overall V DDMIN improvement can be over 300mV in a 128Mb SRAM test-chip.