10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

• Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 178 - 179
• Main Authors: Igarashi, Mitsuhiko, Uemura, Toshifumi, Mori, Ryo, Maeda, Noriaki, Kishibe, Hiroshi, Nagayama, Midori, Taniguchi, Masaaki, Wakahara, Kohei, Saito, Toshiharu, Fujigaya, Masaki, Fukuoka, Kazuki, Nii, Koji, Kataoka, Takeshi, Hattori, Toshihiro
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2014
• Subjects: Central Processing Unit; Clocks; Mobile communication; Random access memory; Synchronization; System-on-chip; Voltage control
• ISBN: 1479909181; 9781479909186
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2014.6757389

The worldwide demand for high-performance mobile or car infotainment application processors (AP) is increasing. This demand coexists with the need for low power to achieve long battery life and avoid thermal runaway. A heterogeneous CPU configuration is an effective solution. The proposed heterogeneous quad/octa-core AP has a combination of high-performance 2GHz cores and energy-efficient 1GHz cores. The maximum performance in the octa-core configuration is 35600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (V t ) and gate lengths (L g ). 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.