8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS

• Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 148 - 149
• Main Authors: Hui Pan, Yuan Yao, Hammad, Mostafa, Junhua Tan, Abdelhalim, Karim, Wang, Evelyn, Hsu, Rick, Yu, Jenny, Aziz, Joseph, Tam, Derek, Fujimori, Ichiro
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2014
• Subjects: CMOS integrated circuits; Mirrors; Solid state circuits; System-on-chip; Topology; Transceivers
• ISBN: 1479909181; 9781479909186
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2014.6757376

Gigabit Ethernet PHY (GPHY) transceivers find wide use in SoCs and standalone PHY chips with hundreds of millions of ports shipped every year. Transceiver design has recently focused on power reduction driven by the need for higher port density and throughput with minimum energy and thermal cost. The line drivers that deliver power from a high voltage supply to remote 100Ω differential loads dominate the GPHY power consumption. The supply voltage determined by the transmit amplitude specs (e.g., 2V ppdiff for 1000BASE-T/100BASE-TX Ethernet) does not scale with technology. This paper presents an architecture that enables rail-to-rail full-duplex operation for high voltage efficiency resulting in a 2.5V GPHY driver in 28nm CMOS that saves 24% power from the mainstream 3.3V drivers.