5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS

• Published in: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 104 - 105
• Main Authors: Gillespie, Kevin, Fair, Harry R., Henrion, Carson, Jotwani, Ravi, Kosonocky, Stephen, Orefice, Robert S., Priore, Donald A., White, Jonathan, Wilcox, Kathryn
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2014
• Subjects: Central Processing Unit; Clocks; CMOS integrated circuits; Logic gates; Metals; Program processors; Transistors
• ISBN: 1479909181; 9781479909186
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2014.6757357

The AMD two-core x86-64 CPU module, codenamed "Steamroller", contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 29.47 mm 2 , which includes two independent integer cores, two instruction decode units and shared instruction fetch, floating-point, and 2MB 16-way L2 cache units (Fig. 5.5.7). Along with the second instruction decode unit, this design includes a larger shared 96KB 3-way instruction cache and a 10KB L2 branch target buffer for improved single-threaded performance and multi-threaded throughput compared to a previous 32nm AMD x86-64 CPU codenamed "Bulldozer" [1].