Copper pillar shape and related stress simulation studies in flip chip packages

One of the major benefits of copper pillar interconnect is to reduce the pillar footprint in comparison to that for traditional solder bumps. This increases the space available for escape routing between neighboring pillars as compared to traditional solder bumps and, in many cases, permits the redu...

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Bibliographic Details
Published in2013 Eurpoean Microelectronics Packaging Conference (EMPC) pp. 1 - 5
Main Authors Ying-Chih Lee, Factor, Bradford, Chin-Li Kao, Yannou, Jean-Marc, Chang-Chi Lee
Format Conference Proceeding
LanguageEnglish
Published IMAPS 01.09.2013
Subjects
Copper
copper pillar bumps
Creep
flip chip
Flip-chip devices
low-k layers
oblong-shaped pillars
Routing
Strain
Stress
stress modeling
Substrates
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Summary:One of the major benefits of copper pillar interconnect is to reduce the pillar footprint in comparison to that for traditional solder bumps. This increases the space available for escape routing between neighboring pillars as compared to traditional solder bumps and, in many cases, permits the reduction of the number of substrate layers and, in turn, reduces the cost of the flip chip package solution. In this paper, we have used finite element analysis to simulate thermo-mechanical stresses in oblong-shaped copper pillars, a configuration which further increases the space available for escape routing. We pay particular attention to the maximum tensile stress at the surface of the dielectric layers on the chip and the solder. We compare three different types of copper pillar cross section geometries: circular, oblong-shape in the radial direction and oblong-shape in the anti-radial direction as well as diameters of polyimide passivation opening under the copper pillar. We find the lowest stress is obtained by using oblong shaped copper pillars in the radial direction in conjunction with a small opening of the polyimide passivation.