Study on high density interconnect with organic build up substrate

For years, many companies or research organizations are concentrating their efforts on further miniaturization and multi-function of devices with high density interconnects. Assembly with 2.5D/3D stacking is one of the most innovative interconnect technologies today, and it is anticipated to be a br...

Full description

Saved in:
Bibliographic Details
Published in2013 Eurpoean Microelectronics Packaging Conference (EMPC) pp. 1 - 5
Main Authors Torii, Takuya, Inoue, Masahiro, Miyamoto, Erina, Hida, Toshinori
Format Conference Proceeding
LanguageEnglish
Published IMAPS 01.09.2013
Subjects
Copper
Flip chip substrate
Interposer
low CTE (the coefficient of thermal expansion)
miniaturization
Resins
Rough surfaces
Substrates
Surface roughness
Surface treatment
Online AccessGet full text

Cover

More Information
Summary:For years, many companies or research organizations are concentrating their efforts on further miniaturization and multi-function of devices with high density interconnects. Assembly with 2.5D/3D stacking is one of the most innovative interconnect technologies today, and it is anticipated to be a breakthrough in the next generation of semiconductor devices. Features required for package substrate is getting more severe in such technology circumstances. For instance, warpage control is one of the challenging parameter, because die or interposer size is bigger and overall thickness target is set without enough margins in most of the cases. Mechanical property close to silicon is preferred to maintain good bump interconnects and control the warpage. Ceramics substrate is considered as a candidate, but there is limitation on miniaturization due to their manufacturing process. Multi-layer organic resin substrate is widely used for semiconductor devise, but CTE value for conventional one is not as low as ceramics or silicon. We evaluated planarity change after the die assembly by using lower CTE resin on both center core and build up layer. We found that newly developed material can reduce the overall substrate CTE and it will prevent it from causing the large warpage. Other technology trend required on packaging substrate is to have finer metal trace as signal I/O density is increasing to add more device function. We have been investigating the technical possibility to manufacture copper metal trace which is less than 8um width. This paper describes the latest status of our development.