A low power 1.2 GS/s 4-bit flash ADC in 0.18 µm CMOS

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used t...

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Bibliographic Details
Published inEast-West Design & Test Symposium (EWDTS 2013) pp. 1 - 4
Main Authors Chahardori, Mohammad, Sharifkhani, Mohammad, Sadughi, Sirous
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Calibration
Clocks
CMOS integrated circuits
Inverters
Partial discharges
Threshold voltage
Transistors
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Summary:A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS process.
DOI:10.1109/EWDTS.2013.6673204