RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns

Hardware/software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-so...

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Bibliographic Details
Published inProceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) pp. 139 - 143
Main Authors Chatha, K.S., Vemuri, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Application specific integrated circuits
Computer architecture
Contracts
Embedded system
Monitoring
Processor scheduling
Read-write memory
Steady-state
System buses
Throughput
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ISBN9780818684425
0818684429
ISSN1092-6100
DOI10.1109/HSC.1998.666251

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Summary:Hardware/software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation.
ISBN:9780818684425
0818684429
ISSN:1092-6100
DOI:10.1109/HSC.1998.666251