A low power D3L 16-bit radix- 4 pipelined SRT divider

In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D 3 L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower p...

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Bibliographic Details
Published in2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) pp. 1 - 6
Main Authors Pourashraf, Shirin, Sayedi, Sayed Masoud
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2012
Subjects
Adders
Clocks
Data Driven Dynamic Logic
Delay
Energy reduction
Latency
MOSFETs
Power demand
Speed
SRT divider
Topology
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ISBN9781467314312
1467314315
ISSN0840-7789
DOI10.1109/CCECE.2012.6335043

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Summary:In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D 3 L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The circuit is designed in TSMC_180 nm CMOS process.
ISBN:9781467314312
1467314315
ISSN:0840-7789
DOI:10.1109/CCECE.2012.6335043