A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS

This paper introduces a flash analog-to-digital converter with high power efficiency. Traditional voltage comparator is replaced by a novel comparison scheme in time domain: analog signal is converted by pulse width modulation block; trigger makes decision by comparing the modulated pulse width. Pro...

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Bibliographic Details
Published in2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
Main Authors Guanzhong Huang, Pingfen Lin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2012
Subjects
Arrays
Capacitance
CMOS integrated circuits
CMOS technology
Power demand
Pulse width modulation
Time domain analysis
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Summary:This paper introduces a flash analog-to-digital converter with high power efficiency. Traditional voltage comparator is replaced by a novel comparison scheme in time domain: analog signal is converted by pulse width modulation block; trigger makes decision by comparing the modulated pulse width. Prototype circuit is designed in a 65-nm logic CMOS technology, achieving a sampling rate of 125-MS/s and an effective number of bits of 4.72. The power consumption is 367-μW under the power supply of 1-V; therefore Figure of Merit at 111-fJ/conversion step is realized.
ISBN:1467325260
9781467325264
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2012.6291942