New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

A 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leaka...

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Bibliographic Details
Published inProceedings of Technical Program of 2012 VLSI Design, Automation and Test pp. 1 - 4
Main Authors Chih-Ting Yeh, Ming-Dou Ker
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2012
Subjects
Clamps
CMOS integrated circuits
CMOS technology
Electrostatic discharges
Leakage current
Logic gates
Thyristors
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Summary:A 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50μm in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.
ISBN:1457720809
9781457720802
DOI:10.1109/VLSI-DAT.2012.6212606