Transistor-level gate model based statistical timing analysis considering correlations

• Published in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 917 - 922
• Main Authors: Qin Tang, Zjajo, A., Berkelaar, M., van der Meijs, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2012
• Subjects: Analytical models; Correlation; Delay; Integrated circuit modeling; Logic gates; Mathematical model

To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propos...