Transistor-level gate model based statistical timing analysis considering correlations

• Published in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 917 - 922
• Main Authors: Qin Tang, Zjajo, A., Berkelaar, M., van der Meijs, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2012
• Subjects: Analytical models; Correlation; Delay; Integrated circuit modeling; Logic gates; Mathematical model
• ISBN: 1457721457; 9781457721458
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2012.6176628

To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45 nm technology. The results demonstrate the high accuracy and speed of our algorithm.