A programmable MEMS-based clock generator with sub-ps jitter performance

• Published in: 2011 Symposium on VLSI Circuits - Digest of Technical Papers pp. 158 - 159
• Main Authors: Lee, F. S., Salvia, J., Lee, C., Mukherjee, S., Melamud, R., Arumugam, N., Pamarti, S., Arft, C., Gupta, P., Tabatabaei, S., Garlepp, B., Hae-Chang Lee, Partridge, A., Perrott, M. H., Assaderaghi, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2011
• Subjects: Clocks; Micromechanical devices; Phase frequency detector; Phase locked loops; Phase noise; Resonator filters

A MEMS-based clock generator achieves sub-ps jitter in 0.18 um CMOS. Key enabling techniques include a 48 MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall o...