A programmable MEMS-based clock generator with sub-ps jitter performance
A MEMS-based clock generator achieves sub-ps jitter in 0.18 um CMOS. Key enabling techniques include a 48 MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall o...
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Published in | 2011 Symposium on VLSI Circuits - Digest of Technical Papers pp. 158 - 159 |
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Main Authors | , , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.06.2011
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Subjects | |
Online Access | Get full text |
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Summary: | A MEMS-based clock generator achieves sub-ps jitter in 0.18 um CMOS. Key enabling techniques include a 48 MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25 MHz achieves an integrated phase jitter of 668 fs rms over an integration bandwidth of 10 kHz-20 MHz. |
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ISBN: | 9781612841755 1612841759 |
ISSN: | 2158-5601 2158-5636 |