Loop distribution for K-loops on Reconfigurable Architectures

• Published in: 2011 Design, Automation & Test in Europe pp. 1 - 6
• Main Authors: Dragomir, O S, Bertels, K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2011
• Subjects: Discrete cosine transforms; Field programmable gate arrays; Hardware; Kernel; Parallel processing; Software algorithms
• ISBN: 9781612842080; 1612842089
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2011.5763245

Within the context of Reconfigurable Architectures, we define a kernel loop (K-loop) as a loop containing in the loop body one or more kernels mapped on the reconfigurable hardware. In this paper, we analyze how loop distribution can be used in the context of K-loops. We propose an algorithm for splitting K-loops that contain more than one kernel and intra-iteration dependencies. The purpose is to create smaller loops (K-sub-loops) that have more speedup potential when parallelized. Making use of partial reconfigurability, the K-sub-loops can take advantage of having more area available for multiple kernel instances to execute in parallel on the FPGA. In order to study the potential for performance improvement of using the loop distribution on K-loops, we make use of a suite of randomly generated test cases. The results show an improvement of more than 40% over previously proposed methods in more than 60% of the cases. The algorithm is also validated with a K-loop extracted from the MJPEG application. A speedup of maximum 8.22 is achieved when mapping MJPEG on VirtexIIPro with partial reconfiguration and 13.41 when statically mapping it on the Virtex-4.