Design for testability, placement and routing of a new oversampled /spl Sigma/-/spl Delta/ modulator

A new top-down design method is proposed in this paper including Verilog hardware description, synthesis, design for testability, library preparation, automatic placement and routing with some artificial interference using a new oversampled /spl Sigma/-/spl Delta/ modulator as an example. A theorem...

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Bibliographic Details
Published in2nd International Conference on ASIC pp. 267 - 270
Main Authors Ye Bo, Huang Lan, Ren Jun-Yan, Zheng Zeng-Yu
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Application specific integrated circuits
Circuit faults
Circuit testing
Clocks
Delta modulation
Design for testability
Design methodology
Hardware design languages
Routing
Very large scale integration
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Summary:A new top-down design method is proposed in this paper including Verilog hardware description, synthesis, design for testability, library preparation, automatic placement and routing with some artificial interference using a new oversampled /spl Sigma/-/spl Delta/ modulator as an example. A theorem is also introduced for DFT consideration.
ISBN:9787543909403
7543909405
DOI:10.1109/ICASIC.1996.562804