8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
We report low V t (V t,Lg=1μm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme sh...
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Published in | 2010 Symposium on VLSI Technology pp. 181 - 182 |
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Main Authors | , , , , , , , , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.06.2010
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Subjects | |
Online Access | Get full text |
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Summary: | We report low V t (V t,Lg=1μm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/μm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained. |
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ISBN: | 9781424454518 1424454514 |
ISSN: | 0743-1562 |
DOI: | 10.1109/VLSIT.2010.5556219 |